
library ieee;
use ieee.std_logic_1164.all;
use work.mystd.all;

entity genSignals is 
	port (
		counterValue: in bus8;			-- vrednost brojaca upravljacke jedinice (ControlUnit)
           
		---------------------------------------------
		-- Upravljacki signali operacione jedinice --
		---------------------------------------------
        
		PCout 		: out std_logic;	
		loadMAR 	: out std_logic;
		incPC 		: out std_logic;
		read 		: out std_logic;
		loadMBRmem	: out std_logic;
		loadIR 		: out std_logic;
		brop 		: out std_logic;
		regsel1 	: out std_logic;
		aluOP 		: out std_logic;
		aluOUT 		: out std_logic;
		outMBRproc 	: out std_logic;
		regIN 		: out std_logic;
		regsel3 	: out std_logic;
		loadMBRproc : out std_logic;
		write 		: out std_logic;
		regsel2 	: out std_logic;
		PCin 		: out std_logic;
		clrIR 		: out std_logic;
		outMAR 		: out std_logic;
		outMBRmem 	: out std_logic;
		reg2M3 		: out std_logic
	); 
     
end genSignals;     
        

architecture genSignals of genSignals is
begin  
		-- signali su aktivni samo u odredjenim koracima
		
		PCout <= '1' when counterValue = X"00" or counterValue = X"1C" OR counterValue = X"22" else '0';
		
		loadMAR <= '1' when counterValue = X"00" OR counterValue = X"06" OR counterValue = X"0C"  else '0';
			
		incPC <= '1' when counterValue = X"01" else '0';
		
		read <= '1' when counterValue = X"01" OR counterValue = X"07" else '0';
		
		loadMBRmem <= '1' when counterValue = X"02" OR counterValue = X"08" else '0';
				
		loadIR <= '1' when counterValue = X"03" else '0';
		
		brop <= '1' when counterValue = X"04" else  '0';
		
		regsel1 <= '1' when counterValue = X"05" OR counterValue = X"0B" OR counterValue = X"10" OR
							counterValue = X"13" OR counterValue = X"16" OR counterValue = X"1C" OR
							counterValue = X"26" OR counterValue = X"22" else '0';
		
		aluOP <= '1' when counterValue = X"05" OR counterValue = X"0B" OR counterValue = X"10" OR
						  counterValue = X"13" OR counterValue = X"16" OR counterValue = X"19" OR
						  counterValue = X"1C" OR counterValue = X"1F" OR counterValue = X"22" OR
						  counterValue = X"26" OR counterValue = X"28" OR counterValue = X"2B" else '0';
						  
		aluOUT <= '1' when counterValue = X"06" OR counterValue = X"0C" OR counterValue = X"11" OR
						   counterValue = X"14" OR counterValue = X"17" OR counterValue = X"1A" OR
						   counterValue = X"1D" OR counterValue = X"20" OR counterValue = X"24" OR
						   counterValue = X"29" else '0';
						   
		outMBRproc <= '1' when counterValue = X"03" OR counterValue = X"09" else '0';
		
		regIN <= '1' when counterValue = X"09" OR counterValue = X"11" OR counterValue = X"14" OR
						     counterValue = X"17" OR counterValue = X"1A" OR counterValue = X"29" else '0';	
				   				  					
		regsel3 <= '1' when counterValue = X"19"   else '0';
		
		loadMBRproc <= '1' when counterValue = X"0D" else '0';
		
		write <= '1' when counterValue = X"0E" else '0';
		
		regsel2 <= '1' when counterValue = X"13" OR counterValue = X"22" else '0';
		
		PCin <= '1' when counterValue = X"1D" OR counterValue = X"20" OR counterValue = X"24" else '0';
		
		clrIR <= '1' when counterValue = X"2E" else '0';
		
		outMAR <= '1' when counterValue = X"01" OR counterValue = X"07" OR counterValue = X"0E" else '0';
		
		outMBRmem <= '1' when counterValue = X"0E" else '0';
				    
		reg2M3 <= '1' when counterValue = X"0D" else '0';
							
end genSignals;








